I’m a fifth-year PhD candidate at UC Davis (graduating December
2026), working with Professor
Jason Lowe-Power on hardware/software co-design for improving
efficiency of memory systems.
My recent work, Pickle,
introduces a highly memory/energy efficient,
core-decoupled data prefetcher for irregular memory accesses. The
prefetch logic is software-defined while prefetch traffic is managed by
the hardware, reflecting how a software engineer would build a data
prefetcher from first principles: predictable in operation, minimal in
overhead, and widely applicable across different data access
patterns.
I’ve spent six years contributing to the gem5 simulator at UC Davis, and
interned at Google as a software engineer and AMD as a researcher.
Research Interests: I began my PhD focused on the
inevitable address translation bottlenecks in
scatter/gather operations of vector
architectures. Over time, I realized this was fundamentally a
data prefetching problem. This insight led to Pickle, a hardware/software
co-designed data prefetcher for irregular memory accesses.
Research
My research focuses on building robust tools for hardware modeling
and identifying the bottlenecks across the hardware/software stack.
[Pickle Prefetcher] I lead the
development of Pickle, a programmable last-level cache data prefetcher.
We demonstrate how to use a simple uncore programmable block to
implement a data prefetcher that yields minimal,
negative in some cases, memory traffic overhead for
irregular memory accesses. This solves the problem of wasted energy due
to the inherent speculative nature of current approaches for irregular
memory accesses.
This project is named after my first cat, Pickle. She loves to play
fetch, tends to take off before I throw the ball (prefetching),
ignores the bad throws (conditional prefetching), and always
catches the ball (perfect prefetch accuracy).
[Choreographer] I drive the development of
Choreographer, a gem5-based framework enabling hardware/software
co-design for near-cache accelerators. We model the full
hardware/software stack, including: out-of-order CPUs, a chiplet-based
on-chip network with a fully detailed MOESI coherence protocol via
gem5’s CHI, and the complete software stack, all in full-system
simulation.
In collaboration with AMD Research.
Pickle is built on Choreographer. I extended the framework to track
the source of every cache miss and measure prefetch usefulness across
the system.
[Pebble Prefetcher] (aka Pickle Premium). More
details later. Probably not prefetching-as-a-service kind of stuff.
Internships
[Google]:
Summer 2026: Platforms/Performance Engineering.
Summer 2025: I profiled and analyzed Borglet’s CPU scheduling on AMD
chips.
Summer 2024: I built a pre-RTL area estimation model for the XLS project. The area model is
used to guide pre-RTL optimizations of some products.
[AMD Research]:
Summer 2023: I built the Choreographer framework.
Previous Work
As an undergrad in Prof. Ian
Davidson’s lab, I collaborated with Zilong Bai on graph-based
unsupervised feature selection, which results in a
SIGKDD paper.
Teaching
I strongly believe that student engagement in classroom and research
comes from a deep understanding of the problem, coupled with a fluency
in using tools (e.g., using software, using facts, and using
abstractions) for problem-solving. The recent emergence of LLMs makes
this foundational understanding and command of tools even more
essential, enabling students to formulate the right
questions for AI assistants and verify the
answers.
Bootcamp Instructor, gem5 Bootcamp, UC Davis (Summer 2022).