Hi, I’m Hoa Nguyen.

Email: hoanguyen@ucdavis.edu
GitHub: https://github.com/hnpl
LinkedIn: https://www.linkedin.com/in/hnpl
GoogleScholar: https://scholar.google.com/citations?user=g6KC_pUAAAAJ

I’m a fourth-year PhD student in the Department of Computer Science at UC Davis. I’m working with Professor Jason Lowe-Power on vector-based acceleration via hardware/software co-design. I also work with Professor Isaac Kim on quantum architectures.

I received my Bachelor’s degree from UC Davis, where I worked for 3+ years as a gem5 software engineer.

During my PhD, I interned for 9 months at AMD Research, where I was responsible for developing the software stack and modeling the performance of an experimental hardware component in gem5. I was also at Google for 3 months, where I built a pre-RTL area estimation model for the XLS project.

Research

My research work involves using the right tools for modeling hardware and writing software for new hardware, with a focus on designing programmer-friendly vector architectures and accelerator designs.

• [Vector] Studying vector-based accelerator designs.
• [Accelerator] Studying accelerator design for irregular memory accesses of HPC/graph-analytics/database applications on vector architectures.
• [Tools] Modifying various parts of a hardware/software stack (e.g., kernel driver, compiler, ISA, hardware simulator) to support new hardware organizations.
• [Tools] Enabling multiple-node full-system simulations via gem5+SST integration.
• [Miscs] Exotic architectures.

Previous Works

I worked at Professor Ian Davidson’s lab in my undergraduate study, during which I co-authored a SIGKDD paper.

Previous Projects

• Enabling gem5 RISC-V full-system simulation with the newer RISC-V software stack.
• Working on gem5’s out-of-order RISC-V Vector instructions execution.
• Implementing support for ARM load-link/store-conditional instructions for FlexCPU, an out-of-order CPU model.
• Implementing RV64IM in Chisel; utilizing spike/riscv-isa-sim for verification.
• Designing a modular write-back multi-way cache system and memory interface in Chisel allowing having an arbitrary number of cache levels.
• Synthesizing the DINOCPU designs using OpenROAD.

Teaching

I strongly believe that student engagement comes from understanding the nature of the problem, and from the fluency of using tools (e.g. using software, using learned facts, and using learned abstractions) for problem solving.

• Bootcamp Instructor, gem5 Bootcamp, UC Davis (Summer 2022).
• Teaching Assistant, Computer Architectures (ECS 154B/ECS 201A), UC Davis (Winter 2022 & 2023).
• Teaching Assistant, Optimization (MAT 168), UC Davis (Spring 2019).
• Teaching Assistant, Abstract Mathematics (MAT 108), UC Davis (Winter 2019).

Open-source Contributions

• gem5
• SageMath
• QEMU
• OpenSBI
• XLS
• Yosys

Other Projects

I ocassionally solve problems at https://projecteuler.net/ and https://rosalind.info/. I like solving problems with geometric interpretations.